1. Field of the Invention
The invention relates to an error handling method of a memory storage device. Particularly, the invention relates to a method for handling program failure, a memory storage device and a memory controller implementing the same.
2. Description of Related Art
Since a flash memory has characteristics of data non-volatility, low power consumption, small volume and non-mechanical structure, etc., it is widely used in various electronic devices. A storage device such as a memory card, a flash drive or a solid state disk, etc. in the market generally uses the flash memory as its storage medium.
FIG. 1 is a schematic block diagram of a conventional flash memory storage device. As shown in FIG. 1, a host system 110 is coupled to the flash memory storage device 120 through a connector 121, so as to read data stored in the flash memory storage device 120 or program data into the flash memory storage device 120. Generally, when the host system 110 wants to program data into the flash memory storage device 120, the data to be written is first written into a buffer memory 1231 of a memory controller 123. Then, the memory controller 123 transmits the data in the buffer memory 1231 to a buffer area 1251 of a flash memory chip 125, and controls the flash memory chip 125 to program data in the buffer area 1251 into a memory cell 1253. After the flash memory chip 125 replies a message indicating that the data has been correctly programmed into the memory cell 1253 to the memory controller 123, the memory controller 123 notifies the host system 100 that the data program operation is completed. When the flash memory chip 125 replies a message indicating a data program failure, the memory controller 123 notifies an error message to the host system 100, and requests the host system 100 to again transmit such batch of data to the memory controller 123. Before the host system 110 receives the notification from the memory controller 123, it cannot send other commands to the flash memory storage device 120. Therefore, the host system 110 has to spend time in waiting for correctly writing data into the memory cell 1253, which may decrease a data processing speed between the host system 110 and the flash memory storage device 120. Therefore, it is a target pursued by those skilled in the art to improve the data processing speed while considering saving the cost.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.